1. FIELD OF THE INVENTION
The present invention relates to an inverter apparatus which incorporates semiconductor devices of self-arc-suppressing type.
2. DESCRIPTION OF THE RELATED ART
FIG. 17 illustrates a known 3-phase 3-level inverter apparatus. This type of 3-level inverter apparatus is disclosed, for example, in IEEE TRANSACTION ON INDUSTRY APPLICATIONS VOL. IA-17, No. 5 1981 "A New Neutral-Point-Clamped PWM Inverter". This 3-level inverter apparatus has self-arc-suppressing type semiconductor devices 1a to 1d connected between a positive electrode P and a negative electrode N of a D.C. power supply 3, and free-wheel diodes 2a to 2d connected in an anti-parallel manner to the semiconductor devices 1a to 1d. Two parallel circuits, each having one semiconductor device and one free-wheel diode, are connected in series as a positive arm between an output terminal A of the inverter apparatus and the positive electrode P of the D.C. power supply 3. Similarly, two parallel circuits, each having one semiconductor device and one free-wheel diode, are connected in series as a negative arm between the output terminal A and the negative electrode N of the D.C. power supply. This 3-level inverter apparatus employs capacitors 4a, 4b as means for dividing the voltage of the D.C. power supply 3. Clamp diodes 5a and 5b are respectively connected between a neutral potential point B of the D.C. power supply 3 and the neutral point C of the positive arm and between the neutral potential point B and the neutral point D of the negative arm.
FIG. 18 illustrates an ordinary 2-level inverter apparatus. Only one phase portion of the apparatus is shown for the purpose of clarification of the drawings. In this inverter, each phase can provide an output which is switchable between the full level and zero level of the D.C. power supply voltage E. In the case of a 3-level inverter apparatus shown in FIG. 19, however, it is possible to obtain, from each phase, an output the level of which is full of the D.C. power supply voltage 2E, an intermediate voltage or zero volt. A description will be given of the operation of this inverter apparatus for producing each level of the 3-level output. When only the self-arc-suppressing type semiconductor devices 1a and 1b are lit on, the positive electrode P of the D.C. power supply and the output terminal A are electrically connected to each other, so that a voltage equal to the full level 2E of the D.C. power supply is obtained at the output terminal A. When only the self-arc-suppressing semiconductor devices 1b and 1c on both sides of the output terminal A are turned on, the neutral potential point B of the D.C. power supply 3 is electrically connected to the output terminal A, so that an intermediate voltage E which is half the full level 2E of the D.C. power supply, is obtained from the output terminal A. When only the self-arc-suppressing type semiconductor devices 1c and 1d of the negative arm are turned on, the negative electrode N of the D.C. power supply 3 and the output terminal A are electrically connected to each other so that zero volt is obtained as the output from the output terminal A.
A GTO thyristor (referred to as GTO, hereafter) can be used as the self-arc-suppressing semiconductor device in the 3-level inverter apparatus of FIG. 19, although such a type of semiconductor device has restriction in voltages and current increase rates. When such a semiconductor device is used, it is necessary to employ a snubber circuit as shown in FIG. 20. More specifically, in FIG. 20, numeral 6 denotes a snubber circuit which is connected in series to the GTO 1 and, hence, called as a series snubber circuit. This series snubber circuit is composed of an anode reactor 7, a diode 8 and a resistor 9. Numeral 10 denotes a snubber circuit which is connected in parallel with the GTO 1 and, hence, is referred to as a parallel snubber circuit. This basic arrangement is disclosed in APPLICATION OF GTO TO VEHICLE PROPULSION CONTROL SYSTEM, Technical Report of Mitsubishi Denki Giho, Vol. 58, No. 12, 1984. In operation, the snubber circuit functions such that, when the GTO 1 is in on state, the anode reactor 7 suppresses the rate of rise of current in the GTO 1 to a desired level while storing energy, whereas, when the GTO 1 has been turned off, a snubber capacitor 11 suppresses the rate of rise of the voltage applied to the GTO 1 to a predetermined value while storing energy. Thus, the snubber circuit functions as a protective circuit which protects GTO 1 from breakdown during switching of the GTO 1. In this snubber circuit, the energy stored in the anode reactor 7 and the energy stored in the snubber capacitor 11 are consumed by resistors 9 and 13, respectively, each time the GTO 1 is switched over.
FIG. 21 shows a 3-level inverter apparatus in which, by way of example, GTOs 1a, 1b, 1c and 1d are used as self-arc-suppressing type semiconductor devices 1a, 1b, 1c and 1d and a parallel snubber circuit of the same type as that denoted by 10 in FIG. 20 is connected in parallel with each GTO. In the circuit shown in FIG. 21, the capacitors 4a, 4b shown in FIG. 17 are substituted by D.C. power supplies 3a and 3b as equivalent components. It is assumed that each of the D.C. power supplies 3a, 3b as the potential-divided source provides a voltage E. From a theoretical point of view, it is possible to suppress the rate of rise of the current in each of the GTOs 1a, 1b, 1c and 1d of the respective phases, by inserting a pair of anode reactors 7a and 7b shown in FIG. 21. In the arrangement shown in FIG. 21, an additional anode reactor 7c is inserted in a line leading from the intermediate potential point B, so that energy stored in all anode reactors 7a, 7b and 7c are temporarily absorbed by voltage clamp circuits 14a, 14b and then charged through and consumed by resistors 17a, 17b. Thus, the GTOs 1a, 1b, 1c and 1d which constitute the 3-level inverter apparatus are switched for producing three output levels as stated before. Energy stored in the reactors and energy stored in the capacitors are consumed by the resistors each time such a switching is performed.
A description will now be given of the operation of the circuit of FIG. 21. Paths or lines mentioned in the following description are collectively shown in FIG. 22. The 3-level inverter apparatus of FIG. 21 has a positive arm constituted by GTOs 1a and 1b and free wheel diodes 2a and 2b, and a negative arm constituted by GTOs 1c and 1d and free wheel diodes 2c and 2d. Numerals 5a and 5b denote clamp diodes. Clamp circuits 14a, 14b are preferably constituted by capacitors 15a, 15b of large capacitance values, diodes 16a, 16b and resistors 17a, 17b. The GTO 1a has a parallel snubber circuit which is composed of a snubber capacitor 11a, a snubber diode 12a and a resistor 13a. Other GTOs 1b, 1c and 1d also are provided with their own snubber circuits. Numerals 7a, 7b and 7c show anode reactors which function as a snubber circuit. Although not shown, an inductive load is connected to 3-level inverter apparatus. It is assumed that the vector of the load current does not change during switching of each GTO 1a, 1b, 1c or 1d.
A description will now be given of the turn-off operation of the GTO 1a. The GTOs 1a and 1b of the positive arm are on, while the GTOs 1c and 1d of the negative arm are off. It is assumed that a load current is flowing from the output terminal A in the direction of an arrow through a line 1 shown in FIG. 22, so that voltage across the snubber capacitor 11a and the voltage across the snubber capacitor 11b are zero, while the voltage across the snubber capacitor 11c and the voltage across the snubber capacitor 11d have been charged up to the divided potentials, i.e., up to the voltage E of the divisions 3a and 3b of the power supply. The following operation is performed when the GTO 1a is turned off from this state to interrupt the load current, followed by turning on of the GTO 1c after elapse of a predetermined short-circuit time. When GTO 1a is turned off, the interrupted current is bypassed to a line 2 so as to charge up the snubber capacitor 11a. When the voltage across the snubber capacitor 11a rises to exceed the voltage E of the D.C. power supply 3, the clamp diode 5a is turned on to become conductive so as to pass the load current via a line 3. In this process, the current from the anode reactor 7a is made to flow through a line 4 so that the energy absorbed in the anode reactor 7a is absorbed by the capacitor 15a. The energy stored in the snubber capacitors 11c, 11d is discharged to the load side through a line 5 via resistors 13c, 13d so as to be consumed by the latter. When the GTO 1c is turned on after elapse of a predetermined time from the turning off of the GTO 1a, energy still remains in the snubber capacitors 11c and 11d, but the energy remaining in the snubber capacitor 11c is completely consumed through the resistor 13c via a line 6, while the snubber capacitor 11d is charged up to the level E of the division of the D.C. power supply. As a consequence, the load current is made to flow through the line 3, so that the energy which has been temporarily stored in the overcharge voltage in the capacitor 15a is discharged through a resistor 17a.
The following operation is performed when the GTO 1b is turned off. It is assumed that the GTOs 1a and 1b of the positive arm are off and on, respectively, while the GTOs 1c and 1d of time negative arm are on and off, respectively, so that a load current flows in the direction of the arrow in the output terminal A past the line 3, and the voltages across the snubber capacitors 11b, 11c are respectively zero, while the snubber capacitors 11a, 11d have been charged up to the level E of the divisions 3a, 3b of the D.C. power supply. It is also assumed that, in the state of the inverter apparatus stated above, the GTO 1b is turned off and, after elapse of a predetermined time thereafter, the GTO 1d is turned on. The current interrupted as a result of turning off of the GTO 1b is made to bypass through a line 7 so as to charge up a snubber capacitor 11b and, when the voltage charged in the capacitor 11b is increase to exceed the level E of the divided source voltage supplied by the D.C. power supply 3b, the free-wheel diodes 2c and 2d are turned on so that the load current flows through the line 8. In this process, the electrical current from the anode reactor 7c is made to flow through a line 9, so that the energy stored in the anode reactor 7c is absorbed by the capacitor 15b. Meanwhile, the energy stored in the snubber capacitor 11d is discharged to the load side through a line 10 via a resistor 13d so as to be consumed by the latter. When the GTO 1d is turned on after elapse of a predetermined time from the turning off of the GTO 1b, if there is any residual energy in the snubber capacitor 11d, such energy is completely consumed by the resistor 13d through a line 11. Consequently, the load current is made to flow through the line 8. In addition, the energy which has over-charged the capacitor 15b is discharged through and consumed by a resistor 17b.
When the GTO 1d is turned off in this state followed by turning on of the GTO 1b after elapse of a time therefrom, the load current starts to be supplied via the line 3, and the energy stored in the snubber capacitor 11b is discharged through a line 12 while being consumed by the resistor 13b until the voltage across this capacitor becomes zero. Meanwhile, the snubber capacitor 11d is charged up to the voltage E of the division 3b of the D.C. power supply through a line 13, and the energy which has been excessively stored in the anode reactors 7b, 7c is absorbed by the capacitor 15b through a line 14. Consequently, the load current is made to flow through the line 3. As a result, the energy which has been temporarily stored in the capacitor 15b as over-charge voltage is discharged through the resistor 17b.
When the GTO 1c is turned on in this state followed by turning on of the GTO 1a after elapse of a predetermined time therefrom, the load current starts to be supplied via the line 1 and the energy stored in the snubber capacitor 11a is discharged through a line 15 while being consumed by the resistor 13a until the voltage across this capacitor becomes zero. Meanwhile, the snubber capacitor 11c is charged up to the voltage E of the division 3a of the D.C. power supply through a line 16, and the energy which has been excessively stored in the anode reactors 7a, 7c is absorbed by the capacitor 15a through a line 17. Consequently, the load current is made to flow through the line 2. As a result, the energy which has been temporarily stored in the capacitor 15a as over-charge voltage is discharged through the resistor 17a.
The switching operations as performed by the GTOs 1a, 1b, 1c and 1d when load current is flowing in the direction reverse to that of arrow in the Figure are not described because they are completely symmetrical to those performed by these GTOs when the current is flowing in the direction of the arrow.
In the known 3-level inverter apparatuses having the described constructions, resistors occupy considerably large part of the components, and the energy stored in capacitors and reactors which are energy accumulating elements of the series and parallel snubber circuits is consumed by these resistors each time the self-arc-suppressing semiconductor element, e.g., GTO, is turned on and off. This undesirably reduces the efficiency of the inverter apparatus, making it difficult to obtain 3-level inverter apparatus operable at higher frequencies, while increasing demand for greater capacity of cooling devices in the inverter apparatus, resulting in an increase in the size of the 3-level inverter itself.